1. Field of the Invention
Example embodiments of the present invention relate to a method of manufacturing a semiconductor device. More particularly, example embodiments of the present invention relate to a method of manufacturing a stacked semiconductor.
2. Description of the Related Art
Recently, the size of semiconductor structures, for example, MOS transistors, and an interval between semiconductor structures has been reduced as design rules of semiconductor devices have been reduced. However, when the size of the semiconductor structures and the interval between the semiconductor structures are continuously decreased on substantially the same plane, resistances of the semiconductor structures may be increased and thus, the semiconductor devices including the semiconductor structures may have relatively poor electrical characteristics.
Conventionally, to solve the above-mentioned problems, a stacked semiconductor device including vertically stacked semiconductor structures has been developed. The stacked semiconductor device may be employed in a static random access memory (SRAM), a system-on-chip (SOC), etc.
In a conventional stacked semiconductor device, because a multi-layered semiconductor structure is vertically stacked, each of channel layers including single crystalline silicon, which may be used for a channel region, may be formed on multi-layered insulation interlayers. The channel layer may be formed by a selective epitaxial growth (SEG) process using a portion of a semiconductor substrate, which may be exposed through an opening of the insulation interlayer, as a seed. Thus, while the channel layer is formed, the opening may be sufficiently filled with a plug including single crystalline silicon.
Further, in a conventional stacked semiconductor device, because the vertically stacked semiconductor structures may be electrically connected to one another, the vertically stacked insulation interlayers may be patterned to form a serial opening exposing a surface of the semiconductor substrate. The serial opening may be filled with a metal wiring, which electrically connects between the semiconductor structures. The serial opening may expose a side face of the channel layer on the insulation interlayer as well as the surface of the semiconductor substrate. Impurity regions, for example, source/drain regions may be formed in the semiconductor substrate and may be electrically connected to the metal wiring.
However, as shown in a conventional device shown of FIG. 1, when the serial opening only exposes the plug on the semiconductor substrate, but not the surface of the semiconductor substrate, and is then filled with the metal wiring, the metal wiring may have a relatively high electrical resistance. The relatively high electrical resistance may be caused by the electrical connection between the metal wiring and the plug. That is, the metal wiring electrically connected to the plug may have a resistance higher than the resistance of a metal wiring electrically connected to the impurity regions in the semiconductor substrate.
On the contrary, as shown in a conventional device of FIG. 2, when a serial opening exposes the surface of the semiconductor substrate and is then filled with the metal wiring, a leakage current through the semiconductor substrate may be generated in the conventional device.
In the conventional device, an etching endpoint for forming the serial opening may be controlled in accordance with a lapse of time. Thus, in a conventional method of manufacturing a stacked semiconductor device, it may be very difficult to form the serial opening exposing the surface of the semiconductor substrate. As a result, the conventional stacked semiconductor device formed using the conventional method may have poor electrical reliability.